1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to a semiconductor device provided with a bipolar transistor and manufacturing method thereof.
2. Description of the Background Art
In recent years, performance of the commercial equipment such as computers has been improved remarkably. The remarkable improvement results in the requirement for a Bi-CMOS (Bipolar Complementary Metal Oxide Semiconductor) structure in which a bipolar transistor and a CMOS transistor are provided on the same semiconductor substrate. This Bi-CMOS structure can have both high performance of the bipolar transistor, and high degree of integration and low power consumption of the CMOS transistor.
The Bi-CMOS structure provided with a bipolar transistor will be described as a conventional semiconductor device.
FIG. 34 is a schematic sectional view showing a structure of the conventional semiconductor device. Referring to FIG. 34, the Bi-CMOS structure has a bipolar transistor region 520, an nMOS transistor region 40 and a pMOS transistor region 60 on the same semiconductor substrate.
In bipolar transistor region 520, an n.sup.+ buried layer 3 is formed at a surface of a p.sup.- silicon substrate 1 made of silicon to which impurity is introduced. On a surface of n.sup.+ buried layer 3, an n.sup.- epitaxial growth layer 5 and an n.sup.+ diffused layer 7 for extracting a collector are formed.
At a surface of n.sup.- epitaxial growth layer 5, a p.sup.- base region 511 and a p.sup.+ external base region 509 are formed adjacent to each other. An n.sup.+ emitter region 513 is formed at a surface of p.sup.- base region 511.
A first interlayer insulating layer 73 is formed so as to cover bipolar transistor region 520. An opening 73a reaching n.sup.+ emitter 513 is formed in first interlayer insulating layer 73. An emitter electrode 519 is formed so as to come into contact with n.sup.+ emitter region 513 through opening 73a. Emitter electrode 519 is formed of polycrystalline silicon to which arsenic (As) has been introduced.
A second interlayer insulating layer 75 is formed on a surface of first interlayer insulating layer 73 so as to cover emitter electrode 519. A contact hole 75a reaching emitter electrode 519 is formed in second interlayer insulating layer 75. An aluminum interconnection layer 81a is formed so as to come into contact with emitter electrode 519 through contact hole 75a.
Contact holes 75b and 75c reaching p.sup.+ external base region 509 and n.sup.+ diffused layer 7, respectively, are formed in first and second interlayer insulating layers 73 and 75. Aluminum interconnection layers 81b and 81c are formed so as to come into contact with p.sup.+ external base region 509 and n.sup.+ diffused layer 7 through contact holes 75b and 75c, respectively.
Then, in nMOS transistor region 40, a p.sup.- well region 33 is formed on the surface of p.sup.- silicon substrate 1. An nMOS transistor 30 is formed at a surface of p.sup.- well region 33.
The nMOS transistor 30 has a pair of n-type source/drain regions 35, a gate oxide film 37 and a gate electrode 39.
The pair of n-type source/drain regions 35 are formed at a prescribed distance away from each other at the surface of p.sup.- well region 33. Each of n-type source/drain regions 35 has an LDD (Lightly Doped Drain) structure consisting of a relatively low concentration n.sup.- impurity region 35a and a relatively high concentration n.sup.+ impurity region 35b. On a region sandwiched between the pair of n-type source/drain regions 35, a gate electrode 39 is formed with a gate oxide film 37 therebetween.
An insulating layer 41 is formed on a surface of gate electrode 39. Sidewall insulating layers 43 are formed so as to cover sidewalls of gate electrode 39.
First and second interlayer insulating layers 73 and 75 are formed so as to cover nMOS transistor 30. Contact holes 75d reaching the pair of n-type source/drain regions 35 are formed in first and second interlayer insulating layers 73 and 75. An aluminum interconnection layer 81d is formed so as to come into contact with the pair of n-type source/drain regions 35 through each of contact holes 75d.
In pMOS transistor region 60, an n.sup.+ buried layer 51 is formed at the surface of p.sup.- silicon substrate 1. An n.sup.- well region 53 is formed on a surface of n.sup.+ buried layer 51. A pMOS transistor 50 is formed at a surface of n.sup.- well region 53.
The pMOS transistor 50 has a pair of p.sup.+ source/drain regions 55, a gate oxide film 57 and a gate electrode 59.
The pair of p.sup.+ source/drain regions 55 are formed at a prescribed distance away from each other at the surface of n.sup.- well region 53. On a region sandwiched between the pair of p.sup.+ source/drain regions 55, gate electrode 59 is formed with gate oxide film 57 therebetween.
An insulating layer 61 is formed on a surface of gate electrode 59. Sidewall insulating layers 63 are formed so as to cover sidewalls of gate electrode 59.
First and second interlayer insulating layers 73 and 75 are formed so as to cover pMOS transistor 50. Contact holes 75e reaching the pair of p.sup.+ source/drain regions 55 are formed in first and second interlayer insulating layers 73 and 75. Aluminum interconnection layers 81e are formed so as to come into contact with p.sup.+ source/drain regions 55 through contact holes 75e.
An oxide film 71 for isolating elements is provided in order to electrically isolate regions 520, 40, 60 and the like.
A method of manufacturing a conventional semiconductor device will now be described.
FIGS. 35-52 are schematic sectional views showing the method of manufacturing the conventional semiconductor device in order. First, referring to FIG. 35, a silicon oxide film 92 having a thickness in the range of 1000 to 3000 .ANG. is formed on the whole surface of p.sup.- silicon substrate 1 by, for example, thermal oxidation. Then, silicon oxide film 92 is patterned to have a desired shape. Antimony (Sb), for example, is implanted into p.sup.- silicon substrate 1 at a dose in the range of 1.0.times.10.sup.15 to 5.0.times.10.sup.15 cm.sup.-2 with about 50 keV using this patterned silicon oxide film 92 as a mask. Then, n.sup.+ layers 3a and 51a are formed at the surface of p.sup.- silicon substrate 1, for example, by performing thermal processing at about 1100.degree. C. for about two hours. Silicon oxide film 92 is then removed.
Referring to FIG. 36, n.sup.- epitaxial growth layer 5 is formed on the whole surface of p.sup.- silicon substrate 1. Thus, a structure in which .sup.+ buried layers 3 and 51 are buried between p.sup.- silicon substrate 1 and n.sup.- epitaxial growth layer 5 is obtained.
Referring to FIG. 37, n-type impurity such as phosphorus (P) is implanted into n.sup.- epitaxial growth layer 5 on n.sup.+ buried layer 51 at a dose of about 1.0.times.10.sup.12 to about 5.0.times.10.sup.12 cm.sup.-2, and are then diffused. Thus, an n.sup.+ well region 53 is formed on n.sup.+ buried layer 51. In addition, p-type impurity such as boron (B) is implanted into a prescribed region of n.sup.- epitaxial growth layer 5 at a dose of about 1.0.times.10.sup.12 to about 5.0.times.10.sup.12 cm.sup.-2, and are then diffused. Thus, a p.sup.- well region 33 is formed adjacent to n.sup.- well region 53.
Referring to FIG. 38, an oxide film 71 for isolating elements is formed at a prescribed region using, for example, LOCOS (Local Oxidation of Silicon).
Referring to FIG. 39, a silicon oxide film (SiO.sub.2) 93 and a silicon nitride film (Si.sub.3 N.sub.4) 94 are stacked in order on the whole surface, with an opening at a prescribed region. Then, a wafer is exposed in an atmosphere containing, for example, POCl.sub.3, using silicon oxide film 93 and silicon nitride film 94 as a mask. Thus, phosphorus is diffused into n.sup.- epitaxial growth layer 5, and an n.sup.+ diffused layer 7 for extracting a collector is formed. Then, silicon nitride film 94 and silicon oxide film 93 are removed successively.
Referring to FIG. 40, a thermal oxidation film 37a is formed on the whole surface by thermal oxidation. Then, polycrystalline silicon film 39a and silicon oxide film 41a both having a thickness of about 2000 .ANG. are stacked in order by LPCVD (Low Pressure Chemical Vapor Deposition). Silicon oxide film 41a and polycrystalline silicon film 39a are patterned by photolithography and etching.
Referring to FIG. 41, gate electrodes 39 and 59 having a desired shape are formed by this patterning.
Referring to FIG. 42, a photoresist 91c is applied to the whole surface, and it is exposed and developed. Thus, a resist pattern 91c which exposes an nMOS transistor region is formed. An n-type impurity such as phosphorus is implanted at a dose of 1.0.times.10.sup.13 to 5.0.times.10.sup.13 cm.sup.-2 with about 50 keV, using resist pattern 91c and gate electrode 39 as a mask. Thus, a relatively low concentration n.sup.- impurity region 35a is formed at the surface of p.sup.- well region 33. Then, resist pattern 91c is removed.
Referring to FIG. 43, after a silicon oxide film is formed so as to cover the whole surface, anisotropic etching is performed on the whole surface of the silicon oxide film. Sidewall oxide films 43 and 63 which cover sidewalls of gate electrodes 39 and 59, respectively, are formed by this anisotropic etching.
Referring to FIG. 44, a photoresist 91d is applied to the whole surface, and it is exposed and developed. Thus, a resist pattern 91d which exposes the nMOS transistor region is formed. An n-type impurity such as arsenic (As) is implanted at a dose of 1.0.times.10.sup.15 to 5.0.times.10.sup.15 cm.sup.-2 with about 50 keV, using resist pattern 91d, gate electrode 39 and sidewall oxide films 43 as a mask. Thus, relatively high concentration n.sup.+ impurity regions 35b are formed at the surface of p.sup.- well region 33. The n-type source/drain region 35 having the LDD structure is constituted by n.sup.- impurity region 35a and n.sup.+ impurity region 35b. Thus, nMOS transistor 30 is formed. Then, resist pattern 91d is removed.
Referring to FIG. 45, a photoresist 91e is applied to the whole surface, and it is exposed and developed. Thus, a resist pattern 91e which exposes a pMOS transistor region and a prescribed region of a bipolar transistor is formed. A p-type impurity such as BF.sub.2 is implanted into n.sup.- well region 53 and n.sup.- epitaxial growth layer 5 at a dose of 1.0.times.10.sup.15 to 5.0.times.10.sup.15 cm.sup.-2 with about 50 keV, using resist pattern 91e as a mask. Thus, a p.sup.+ source/drain region 55 is formed in the pMOS transistor region, and a p.sup.+ external base region 509 is formed in the bipolar transistor region. Thus, a pMOS transistor 50 is formed. Then, resist pattern 91e is removed.
Referring to FIG. 46, a photoresist 91f is applied to the whole surface, and it is exposed and developed. Thus, a resist pattern 91f which exposes a prescribed region of the bipolar transistor region is formed. A p-type impurity such as BF.sub.2 is implanted into n.sup.- epitaxial growth layer 5 at a dose of about 1.0.times.10.sup.14 cm.sup.-2 with about 40 keV, using resist pattern 91f as a mask. Then, thermal processing is performed at a temperature, for example, of 800.degree. C. for about 30 minutes. Thus, a p.sup.- base region 511 adjacent to p.sup.+ external base region 509 is formed with a junction depth from the surface of about 0.1 to 0.3 .mu.m. Then, resist pattern 91f is removed.
Referring to FIG. 47, a first interlayer insulating layer 73 made, for example, of a silicon oxide film having a thickness of about 2000 .ANG. is formed on the whole surface.
Referring to FIG. 48, after a photoresist 91g is applied to the whole surface, it is exposed and developed. Thus, a resist pattern 91g having a desired shape is formed. RIE (Reactive Ion Etching), for example, is performed on first interlayer insulating layer 73, using resist pattern 91g as a mask. Thus, an opening 73a which exposes a portion of a surface of p.sup.- base region 511 is formed in first interlayer insulating layer 73. Then, resist pattern 91g is removed.
Referring to FIG. 49, a polycrystalline silicon film 519a having a thickness of about 2000 .ANG. is formed on the whole surface by, for example, LPCVD. Arsenic of about 5.times.10.sup.15 cm.sup.-2 is implanted into the whole surface of polycrystalline silicon film 519a with about 60 keV. Thermal processing is performed on polycrystalline silicon film 519a into which impurity is introduced (hereafter referred to as a doped polycrystalline silicon film) at a temperature, for example, of 800.degree. to 850.degree. C. for about 30 minutes.
Referring to FIG. 50, under the thermal processing, arsenic in the doped polycrystalline silicon film is diffused into p.sup.- base region 511, and an n.sup.+ emitter region 513 is formed. Then, doped polycrystalline silicon film 519a is patterned and an emitter electrode 519 is formed.
Referring to FIG. 51, a second interlayer insulating layer 75 is formed on the whole surface of first interlayer insulating layer 73 so as to cover emitter electrode 519. Contact holes 75a, 75b, 75c, 75d and 75e are formed in first and second interlayer insulating layers 73 and 75 by photolithography and etching.
Referring to FIG. 52, aluminum interconnection layers 81a, 81b, 81c, 81d and 81e are formed so as to come into contact with conductive regions or the like of the lower layer through contact holes 75a, 75b, 75c, 75d and 75e, respectively.
In order to improve the degree of integration and performance of a semiconductor device according to scaling, reduction in the size of a transistor, in particular, of a gate length of a MOS transistor is required. If the gate length is reduced, distance between the source/drain regions becomes small and punch through is more likely to occur. In order to prevent punch through, diffusion of the impurity elements at the source/drain region must be suppressed. Thus, quantity of heat provided by thermal processing which is performed after the formation of a transistor must be reduced.
On the other hand, the improvement in performance of the bipolar transistor requires reduction in base width W.sub.B shown in FIG. 53. FIG. 53 is an enlarged sectional view schematically showing the bipolar transistor region of FIG. 34.
The value of cut-off frequency f.sub.T is generally used as one index of performance, in particular, of high-speed performance of the bipolar transistor. The value f.sub.T is given by the following equation: ##EQU1## where Dn is diffusion coefficient of electrons and W.sub.B is the base width.
According to the above equation, the cut-off frequency f.sub.T is inversely proportional to the square of the base width W.sub.B. Thus, if the base width W.sub.B is reduced, the value of the cut-off frequency f.sub.T is increased, resulting in the improvement in performance of the bipolar transistor.
However, if thermal processing is performed at a high temperature for a long time after the formation of the bipolar transistor, the base width W.sub.B will become large. This results from the fact that the diffusion rate of boron, i.e. impurity in the base region, is higher than that of arsenic, i.e. impurity in the emitter region. That is, the base region extends widely, while the emitter region extends not as much as the base region, resulting in the large base width W.sub.B.
Thus, reduction in quantity of heat provided by thermal processing is necessary also for the improvement in performance of the bipolar transistor.
In the conventional semiconductor device, crystal defects are introduced, when the base region 511 is formed by implantation of BF.sub.2 ions shown in FIG. 46.
FIG. 54 is a schematic sectional view showing how the crystal defects are introduced by implantation of BF.sub.2 ions. Referring to FIG. 54, ion implantation is a technique of physically implanting ions into a substrate. Thus, implanted ions collide with atoms of crystal in the substrate and a number of crystal defects 95 are produced.
Crystal defects 95 can be repaired by thermal processing at a high temperature of 900.degree. C. or more after the base region is formed. However, such a thermal processing at a high temperature causes punch through in the MOS transistor and degradation of performance in the bipolar transistor.
If thermal processing is performed at the temperature of at most about 850.degree. C. after ion implantation to the base so as to reduce quantity of heat provided by the thermal processing at a high temperature, crystal defects 95 produced by the ion implantation will not be repaired.
FIG. 55 is a schematic sectional view showing the state where defects are distributed in the base region. Referring to FIG. 55, if n.sup.+ emitter region 513 is formed containing crystal defects 95, crystal defects 95 will be distributed near the junction of n.sup.+ emitter region 513 and p.sup.- base region 511. There is produced a depletion layer in the junction, and if crystal defects 95 are distributed in the depletion layer, current will leak from crystal defects 95. That is, leak current of emitter-base junction will increase.
FIG. 56 is a graph showing characteristics of the bipolar transistor, which is referred to as Gummel Plot. In this graph, the ordinate indicates base current I.sub.B (current extracted from a base electrode) and collector current I.sub.C (current extracted from a collector electrode), and the abscissa indicates voltage VBE applied to the base-emitter junction.
Referring to FIG. 56, if the leak current of the emitter-base junction increases, leak current of the base current I.sub.B will increase on lower voltage side (lower values of V.sub.BE). Increase in the value of the base current I.sub.B for the lower voltages will cause significant decrease in current amplification efficiency h.sub.FE (=I.sub.I /I.sub.B) for lower values of the collector current I.sub.C, as shown by the dotted line in FIG. 57.
That is, a prescribed current amplification efficiency h.sub.FE can be obtained only when a high voltage is applied to the base-emitter junction. Thus, in order to obtain the prescribed current amplification efficiency h.sub.FE, time to increase the voltage applied to the base-emitter junction to a high value is necessary, and operation speed will be delayed correspondingly. Thus, if the leak current at the emitter-base Junction increases, the operation speed of the bipolar transistor, in which high-speed operation is required, becomes slower.